1. Field of the Invention
This invention relates to integrated circuit manufacture and more particular to a capacitor with enhanced area and dielectric formed by implantation of conductive and insulative layers within a polysilicon material.
2. Background of the Relevant Art
A capacitor is an electronic component capable of storing electrical energy. A capacitor consists of two conductive plates insulated from each other by a dielectric. The capacitance value is determined by the following formula: EQU C=kA/t
where, C=Coulombs/Volt (Farad), k=dielectric constant of the insulator, A=area of overlay of the plates, and t=thickness of the dielectric
Capacitors can be configured in many ways. The plates and adjacent dielectrics can take on a planar shape, a trenched shape, a stacked shape or a fin shape. A planar capacitor entails a dielectric placed between a pair of planar conductors, wherein the conductors can be polysilicon and/or silicon. The polysilicon and silicon are generally formed on or near the substrate topography. Each side of the plate is electrically connected to other active devices formed upon the substrate to complete the connection. In high density applications, capacitors are sometimes laid out in a trench such that the insulative and conductive regions extend into the substrate instead of across the substrate. A trench capacitor thereby occupies a substrate area roughly equal to the thickness of the dielectric and adjoining plates rather than the area of the plates. Another way in which to conserve substrate area is to stack the capacitor on top of the transistors to which they are connected. Stacking of capacitors was favorably introduced in DRAM applications where conservation of area is crucial. It is understood that "capacitor" set forth herein below comprises electrically conductive plates spaced from each other by an insulative material, wherein the plates and insulative material are arranged in a planar, trenched or stacked configuration.
An examination of capacitance value C indicates that in order to increase the capacitance, dielectric constant k and/or area A must be increased or, conversely, thickness t must be decreased. A majority of plated capacitors utilize silicon nitride as a preferred dielectric material. Silicon nitride is generally deposited from a chemical vapor deposition (CVD) chamber onto the lower conductive plate. The CVD reaction used for preparing high-temperature silicon nitride is as follows: 3SiH.sub.4 +NH.sub.3 .fwdarw.Si.sub.3 N.sub.4 +12H.sub.2. Silicon nitride is relatively impermeable to oxygen (as well as phosphorous and boron) and provides an efficient barrier against diffusion between the plates. More importantly, silicon nitride has a dielectric constant K much higher than, for example, silicon dioxide. While silicon nitride is the preferred dielectric, silicon nitride often exhibits numerous pinholes which may or may not extend through the nitride. Regardless of the CVD techniques used, silicon nitride remains more prone to pinholes that other dielectrics. Pinholes, resulting from deposition, must be avoided in order to ensure the conductive plates do not short to one another.
If the designer wishes to increase capacitance by decreasing dielectric thickness t, then he or she must address the problem of pinholes. As the deposited layer of silicon nitride becomes thinner, the propensity for catastrophic pinholes increases. Thus, a trade-off exists between dielectric enhancement (thickness minimization) and the presence of pinholes. Existing silicon nitride layers require a dielectric thickness placed upon the lower plate of generally more than 100 Angstroms in order to prevent substantial occurrence of pinholes. After the silicon nitride is deposited, a wet oxidation step is used to fill the pinholes. Thereafter, a second conductive plate of, for example, polysilicon is deposited over the silicon nitride dielectric to complete the plated capacitor configuration. Accordingly, conventional capacitors utilize four deposition steps: a first conductive deposition step, followed by an insulative deposition step, followed by a wet oxide step, followed by a second conductive deposition step. All four steps require two separate masking and photolithography steps thereby adding to the complexity of the manufacturing process. Moreover, the plated structure results in a relatively thick combination of conductive and insulative layers which, if placed on an even substrate surface, substantially adds to the unevenness of the circuit topography. Subsequent planarization steps involving selective removal of overlaying oxide and/or application of spin-on glass (SOG) are needed to re-planarize the upper surface.
In addition to increasing dielectric constant K and/or decreasing thickness t, capacitance C can be increased by increasing area A. Recent work has been performed in the area of texturization, in which additional area is provided at the juncture between the insulative layer and one of the adjacent conductive layers. Specifically, the conductive layer can be texturized after it has been deposited by growing a sacrificial oxide upon the upper surface of the conductive (generally polysilicon) layer. Doping of the underlying polysilicon prior to oxide growth enhances oxide growth rate and, when performed at a specific temperature, leads to a roughness or texture in the areas at which oxide is grown. Oxide grown upon the exposed surface of the deposited polysilicon is then removed leaving a roughened or textured upper surface on which silicon nitride is subsequently placed. The method of polysilicon texturization to enhance capacitor surface area is well studied and set forth in U.S. Pat. Nos. 5,043,780 to Fazan, et al.; 5,082,797 to Ghan, et al.; 5,102,832 to Tuttle; 5,138,411 to Sandhu; 5,191,509 to Wen; and 5,208,176 to Ahmad, et al. All of the above teach the importance of texturization, but in the context of depositing a polysilicon layer to be textured followed by deposition of a dielectric and another polysilicon thereover. For reasons stated above, deposition of separate layers not only is time consuming, costly and burdensome, but also increases the chances of pinholes existing in the dielectric as well as gross contamination occurring on the textured polysilicon before silicon nitride deposition. Any pinholes or contamination (which can lead to pinholes) existing within the dielectric will deleteriously effect capacitor performance regardless of any advantages of texturization. Accordingly, it would be advantageous to provide a processing methodology in which a capacitor is formed absent deposition of each layer (conductive and insulative layers). It would be further desirable to obtain the benefits of silicon nitride, as the dielectric at textured junctures, without having to undergo the disadvantages of pinholes, contamination, and added processing steps associated with layer-by-layer deposition.